John J Bulzacchelli, Age 85301 Baltimore Blvd, Wall Township, NJ 08750

7733984, Jun 8, 2010

Nov 8, 2006

11/557695

Steven John Baumgartner - Zumbro Falls MN, US
Anthony Richard Bonaccio - Shelburne VT, US
John Francis Bulzacchelli - Yonkers NY, US
Daniel Mark Dreps - Georgetown TX, US

International Business Machines Corporation - Armonk NY

H04L 27/00

375324, 375308

A method for implementing phase rotator circuits and phase rotator circuit of the invention includes a polyphase filter network to create a quadrature phase version of the input signal. The polyphase filter network is partitioned into a first part that is physically isolated from the phase rotator circuit and a second part that is embedded in the phase rotator circuit. The second part of the polyphase filter is coupled to the first part of the polyphase filter by a high-pass equalizing buffer stage. The second part of the polyphase filter is coupled to the phase rotator circuit by a bandlimiting buffer stage.

7792185, Sep 7, 2010

Feb 7, 2007

11/672309

John Francis Bulzacchelli - Yonkers NY, US
Matthew J. Park - Cambridge MA, US

International Business Machines Corporation - Armonk NY

H03H 7/30

375233

Methods and apparatus are disclosed for calibrating summing amplifiers based on current integration. For example, apparatus for calibrating output voltage levels of a current-integrating summing amplifier includes the following components. A duplicate integrator circuit is provided, wherein the duplicate integrator circuit replicates an integrator circuit of the current-integrating summing amplifier. A comparing circuit, coupled to the duplicate integrator circuit, is provided for comparing at least one output voltage level generated by the duplicate integrator circuit with a reference voltage level. A feedback loop circuit, coupled to the comparing circuit and the duplicate integrator circuit, is provided for adjusting at least one bias signal of the duplicate integrator circuit so that the output voltage level generated by the duplicate integrator circuit matches the reference voltage level, wherein the bias signal is applied to the integrator circuit of the current-integrating summing amplifier thereby calibrating output signal components due to multiple input signals of the current-integrating summing amplifier.

7792187, Sep 7, 2010

Aug 31, 2007

11/848477

John F. Bulzacchelli - Yonkers NY, US

International Business Machines Corporation - Armonk NY

H03K 5/159

375233, 375231, 375232

A decision feedback equalizer (DFE) and method include summer circuits to add a dynamic feedback signal representing a dynamic feedback tap to a received input and to speculate on a speculative tap. Data slicers are configured to receive outputs of the summer circuits and sample the outputs of the summer circuits. First multiplexers are included, each of which is configured to receive a first input from a corresponding data slicer. Second multiplexers are included, each of which is configured to receive an output of a plurality of the first multiplexers. The second multiplexers have an output fed back to a second input of the first multiplexers, and the second multiplexer output is employed to provide a select signal for a second multiplexer on a different section of the DFE and to drive the dynamic feedback signal to a summer circuit on a same section of the DFE.

7822114, Oct 26, 2010

Jun 12, 2007

11/761586

John F. Bulzacchelli - Yonkers NY, US
Daniel J. Friedman - Sleepy Hollow NY, US
Alexander Rylyakov - Mount Kisco NY, US
Koon Lun Jackie Wong - Irvine CA, US

International Business Machines Corporation - Armonk NY

H03H 7/30

375233, 375229

A decision feedback equalizer (DFE) and method include at least two paths. Each path includes the following. An adder is configured to sum an input with a first feedback tap fed back from a different path. A latch is coupled to the adder to receive a summation signal as input. The latch includes a transparent state, and an output of the latch is employed as the first tap in a feedback path to an adder of a different path, wherein a partially resolved first tap in the feedback path is employed during the transparent state to provide a soft decision to supply correction information in advance of a hard decision of the latch.

7893861, Feb 22, 2011

Jun 30, 2009

12/494496

John F. Bulzacchelli - Yorktown Heights NY, US
Daniel J. Friedman - Yorktown Heights NY, US
Shahrzad Naraghi - Austin TX, US
Sergey V. Rylov - Yorktown Heights NY, US
Alexander V. Rylyakov - Yorktown Heights NY, US

International Business Machines Corporation - Armonk NY

H03M 1/50

341166, 341155

Apparatus and methods are provided relating to time-to-digital based analog-to-digital converter. An apparatus includes a time-to-digital converter based analog-to-digital converter for generating a first signal and a second signal having a timing relationship between a rising edge of the first signal and a rising edge of the second signal based on a sampled input analog voltage level, and converting the timing relationship into a corresponding time-to-digital representation. The time-to-digital representation is obtained without any voltage comparison and current comparison.

8085841, Dec 27, 2011

Apr 2, 2008

12/061268

John F. Bulzacchelli - Yonkers NY, US
Timothy O. Dickson - Danbury CT, US
Daniel J. Friedman - Sleepy Hollow NY, US
Alexander V. Rylyakov - Mount Kisco NY, US

International Business Machines Corporation - Armonk NY

H04L 27/01

375233, 375229, 375230, 375232

A decision feedback equalizer (DFE) and method including a branch coupled to an input and including a sample-and-hold element configured to receive and sample a received input signal from the input and a current-integrating summer. The current-integrating summer is coupled to an output of the sample-and-hold element. The summer is configured to receive and sum currents representing at least one previous decision and an input sample. The at least one previous decision and the input sample are integrated onto a node, wherein the input sample is held constant during an integration period, thereby mitigating the effects of input transitions on an output of the summer.

8138840, Mar 20, 2012

Jan 23, 2009

12/358736

Herschel A. Ainspan - New Hempstead NY, US
John F. Bulzacchelli - Yonkers NY, US
Zeynep Toprak Deniz - Glen Oaks NY, US
Daniel J. Friedman - Sleepy Hollow NY, US
Alexander V. Rylyakov - Mount Kisco NY, US
Jose A. Tierno - Stamford CT, US

International Business Machines Corporation - Armonk NY

H03L 7/085
H03L 7/089

331 1A, 331 16, 331 34, 331 36 C, 375376

A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference clock signal with a feedback clock signal to determine phase and frequency differences between the dithered reference clock signal and the feedback clock signal. A digitally controlled oscillator (DCO) is configured to receive early or late determinations from the PFD to adjust an output in accordance therewith, wherein the dithered reference clock signal distributes jitter response to enhance overall operation of the DPLL.

8183948, May 22, 2012

Feb 9, 2010

12/702798

Herschel A. Ainspan - Yorktown Heights NY, US
John F. Bulzacchelli - Yorktown Heights NY, US
Daniel J. Friedman - Yorktown Heights NY, US
Ankush Goel - Los Angeles CA, US
Alexander V. Rylyakov - Yorktown Heights NY, US

International Business Machines Corporation - Armonk NY

H03B 5/12
H03B 5/18

331167, 331 46, 331117 FE

A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible.