John J Derosa, Age 685963 E Teton Cir, Mesa, AZ 85215

6928500, Aug 9, 2005

Jun 26, 1997

08/883118

Raj Ramanujan - Leominster MA, US
James B. Keller - Arlington MA, US
William A. Samaras - Haverhill MA, US
John Derosa - Princeton MA, US
Robert E. Stewart - Stow MA, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F013/14
G06F013/36

710107, 710112, 710305, 710240

A high speed bus system for use in a shared memory system that allows for the high speed transmissions of commands and data between a number of processors and a memory array of a multi-processor, shared memory system, with the high speed bus system including a central unit and a series of uni-directional buses that connect between the plurality of processors and shared memory, with the central unit including arbitration logic and a series of multiplexers to determine which CPUs are granted access to shared buses, scheduling logic that works with the arbitration logic and multiplexers to determine which CPUs are granted access to the shared buses, and port logic for combining the CPU transmissions and determining if such transmissions are valid.

7668997, Feb 23, 2010

Jun 14, 2005

11/152213

Raj Ramanujan - Leominster MA, US
James B. Keller - Arlington MA, US
William A. Samaras - Haverhill MA, US
John DeRosa - Princeton MA, US
Robert E. Stewart - Stow MA, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 12/00

710240, 710241

An apparatus comprises a plurality of ports wherein each port is adapted to couple to a device. At least one port connects by way of first and second unidirectional, point-to-point communication links with a device. The first unidirectional, point-to-point communication link transfers data from the device to the central logic unit and the second unidirectional, point-to-point communication link transfers data from the central logic unit to the device.

5160922, Nov 3, 1992

Jun 29, 1990

7/546556

John DeRosa - Princeton MA
Lauren M. Hagstrom - Worcester MA
Lon S. Hilde - Lunenburg MA
Oren Wiesler - Acton MA

Digital Equipment Corporation - Maynard MA

G06F 1300

3408255

A system and method for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit for the chip during a short, predetermined time window by dynamically arbitrating request signals from discrete on-chip logic elements for assignment of output pins according to the priority of the request signals based on the type and intended use of output signals from such elements, and the immediate state of the integrated circuit chip.

4742451, May 3, 1988

May 21, 1984

6/612621

William F. Bruckert - Hudson MA
Tryggve Fossum - Northboro MA
John A. DeRosa - Princeton MA
Richard E. Glackemeyer - Bolton MA
Allan E. Helenius - Westford MA
John C. Manton - Marlboro MA

Digital Equipment Corporation - Maynard MA

G06F 942

364200

A central processor unit for a digital data processing system that processes prefetched instructions including a conditional branch instruction. The processor includes a fetch unit that has separate portions, one that retrieves operands and the other that retrieves instructions. When the fetch unit fetches a conditional branch instruction, it may continue to prefetch "branch not taken" instructions using the instruction fetch portion. The fetch unit initially uses the operand fetch portion to prefetch "branch taken" instructions. If it is determined that the branch is not taken, the prefetch operation is aborted, otherwise the prefetch operation is allowed to continue to provide the next instruction used by the processor.