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John J Laurence, Age 6018956 W 87Th Ln, Arvada, CO 80007

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Known as:
John Joseph Laurence John L Laurence John Laurence Revocable Tr John J Lawrence

John Laurence Phones & Addresses

18956 W 87Th Ln, Arvada, CO 80007

11837 Utica St, Westminster, CO 80031 (303) 386-4798 (720) 887-8279

Broomfield, CO

Erie, CO

Niwot, CO

Boulder, CO

Work

Company: Baylor scott and white health system Oct 2012 Position: Administrator of general surgery division

Education

School / High School: Texas A&M University: Health Sciences School of Rural Public Health- College Station, TX Jan 2006 Specialities: MHA in Masters of Healthcare Administration

Mentions for John J Laurence

John Laurence resumes & CV records

Resumes

John Laurence Photo 42

John Laurence

Location:
Baker City, Oregon
Industry:
Renewables & Environment
John Laurence Photo 43

John Laurence

John Laurence Photo 44

John Laurence - College Station, TX

Work:
Baylor Scott and White Health System Oct 2012 to 2000
Administrator of General Surgery Division Buckley AFB - Denver, CO May 2009 to Jun 2012
Director of Operations as Group Practice Manager Palmer Ranch - Sarasota, FL Feb 2005 to Jul 2006
Project Coordinator The Glenridge The Glenridge on Palmer Ranch - Sarasota, FL Aug 2004 to Feb 2005
Administrator in Training Administration on Aging - Washington, DC Sep 2002 to Dec 2002
Programs Department Internship Fleet Landing - Atlantic Beach, FL Jun 2001 to Jul 2001
Internship
Education:
Texas A&M University: Health Sciences School of Rural Public Health - College Station, TX Jan 2006 to Jan 2008
MHA in Masters of Healthcare Administration University of North Texas - Denton, TX Jan 2003 to Jan 2005
M.S in Administration of Long Term Care/Retirement Communities w/ case mediation certification Texas A&M University - College Station, TX Jan 1997 to Jan 2002
B.S. in Agriculture Development with minor in Business

Publications & IP owners

Us Patents

Implementation Set-Based Guide Engine And Method Of Implementing A Circuit Design

US Patent:
7171644, Jan 30, 2007
Filed:
Aug 6, 2004
Appl. No.:
10/912957
Inventors:
John J. Laurence - Westminster CO, US
Daniel J. Downs - Longmont CO, US
Raymond Kong - San Francisco CA, US
Richard Yachyang Sun - Mountain View CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 18, 716 2
Abstract:
A method of implementing an integrated circuit design can include the steps of forming a base implementation set and forming a guide implementation set having a plurality of guide implementation set nodes. The method can further include the steps of depositing directives on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of creating and depositing tasks on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of invoking each task deposited on guide implementation set nodes as each node in the guide implementation set tree is visited.

Method And System For Designing Integrated Circuits Using Implementation Directives

US Patent:
7181704, Feb 20, 2007
Filed:
Aug 6, 2004
Appl. No.:
10/913746
Inventors:
Daniel J. Downs - Longmont CO, US
Raymond Kong - San Francisco CA, US
John J. Laurence - Westminster CO, US
Sankaranarayanan Srinivasan - Boulder CO, US
Richard Yachyang Sun - Mountain View CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 3, 716 4, 716 11, 716 17, 716 18
Abstract:
A method of designing an integrated circuit using implementation directives for flow control can include the step of loading a design along with specified constraints, creating at least one instance of an data structure formed from a partial netlist, and decomposing at least one set of high level rules into simple implementation directives. The method can further include the steps of selectively attaching the simple implementation directives to the data structure, implementing a task manager which queries a data structure node to create a list of tasks to be performed on the data structure, and executing the list of tasks using a generic flow engine.

Method And System For Managing Behavior Of Algorithms

US Patent:
7290241, Oct 30, 2007
Filed:
Aug 6, 2004
Appl. No.:
10/913752
Inventors:
Daniel J. Downs - Longmont CO, US
John D. Bunte - Westminster CO, US
Raymond Kong - San Francisco CA, US
John J. Laurence - Westminster CO, US
Richard Yachyang Sun - Mountain View CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 18
Abstract:
A method of managing behavior of algorithms includes specifying governing rules/policies that manage I-Set implementation directives, command line options, and environment variables and loading governing rules/policies into a behavior manager. Inside a client tool, the I-Set hierarchy processes and iterates one I-Set node at a time. Without more I-Sets to process, the method is done. If more, then the tool queries the Behavior Manager with an I-Set with symbolic designators of the queried behavior. The Behavior Manager can reply to the client tool indicating whether the queried behavior is to be supported on the appropriate logic of the I-Set node. If the algorithm for the I-Set node lacks the queried behavior, then another I-Set might require processing. If the algorithm for the I-Set node has the queried behavior, then the client tool applies the corresponding algorithm(s) on the appropriate logic.

Method And Arrangement Providing For Implementation Granularity Using Implementation Sets

US Patent:
7360177, Apr 15, 2008
Filed:
Aug 6, 2004
Appl. No.:
10/913000
Inventors:
Raymond Kong - San Francisco CA, US
Daniel J. Downs - Longmont CO, US
John J. Laurence - Westminster CO, US
Richard Yachyang Sun - Mountain View CA, US
Sankaranarayanan Srinivasan - Boulder CO, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 1, 716 7, 716 8, 716 12, 716 16, 716 18
Abstract:
A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.

Method And Arrangement Providing For Implementation Granularity Using Implementation Sets

US Patent:
8141010, Mar 20, 2012
Filed:
Feb 8, 2008
Appl. No.:
12/028337
Inventors:
Raymond Kong - San Francisco CA, US
Daniel J. Downs - Longmont CO, US
John J. Laurence - Westminster CO, US
Richard Yachyang Sun - Mountain View CA, US
Sankaranarayanan Srinivasan - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716100, 716101
Abstract:
A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.

Method And Arrangement Providing For Implementation Granularity Using Implementation Sets

US Patent:
8296690, Oct 23, 2012
Filed:
Feb 7, 2008
Appl. No.:
12/027501
Inventors:
Raymond Kong - San Francisco CA, US
Daniel J. Downs - Longmont CO, US
John J. Laurence - Westminster CO, US
Richard Yachyang Sun - Mountain View CA, US
Sankaranarayanan Srinivasen - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716100, 716103, 716104, 716105, 716110, 716116, 716119, 716122
Abstract:
A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.

Method And System For Implementing A Circuit Design In A Tree Representation

US Patent:
7146583, Dec 5, 2006
Filed:
Aug 6, 2004
Appl. No.:
10/912999
Inventors:
Richard Yachyang Sun - Mountain View CA, US
Daniel J. Downs - Longmont CO, US
Raymond Kong - San Francisco CA, US
John J. Laurence - Westminster CO, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 3, 716 16
Abstract:
A method of implementing a user integrated circuit (IC) design in a tree representation includes the step of introducing the tree representation for the user IC design in a partitioned manner including at least one sub-design to form a design abstraction of the user design. At least one sub-design can include a sub-design providing for multiple levels of implementation hierarchy. The method can further include the step of traversing the design abstraction in a top-down fashion to provide functions selected among floor planning, port assignment, and timing budgeting for at least one sub-design, and the step of traversing the design abstraction in a bottom-up fashion to facilitate at least one among resolution of resource conflicts and parallel processing of multiple sub-designs. Traversing the design abstraction in the bottom-up fashion can facilitate a re-budgeting of timing for the integrated circuit design.

Isbn (Books And Publications)

The Seeds Of Disaster: A Guide To The Realities, Race Policies And World-Wide Propaganda Campaigns Of The Republic Of South Africa

Author:
John Laurence
ISBN #:
0575000422

A History Of Capital Punishment: With Special Reference To Capital Punishment In Great Britain

Author:
John Laurence
ISBN #:
0804611149

Gardening Improv'D

Author:
John Laurence
ISBN #:
0824001575

Possible Relatives

David Laurence  Deborah L Laurence  Dennis L Laurence  Erin B Laurence  Gregory M Laurence  Jack C Laurence  Janet M Laurence  John J Last  John J Stan  John C Stanaway 

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