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John S Mangan, Age 6611132 Tabeaud Rd, Pine Grove, CA 95665

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Known as:
John Stephen Mangan Beth H Mangan John S Magnan John Morgan Beth Hix
Related to:
Wendy L Mangan 44

John Mangan Phones & Addresses

11140 Tabeaud Rd, Pine Grove, CA 95665 (831) 430-0107

Roanoke, IL

2158 Sunny Acres Dr, Santa Cruz, CA 95060

319 Chirco Ave, Santa Cruz, CA 95065 (408) 475-8129

5025 Winkle Ave, Santa Cruz, CA 95065

Lakewood, CO

Broomfield, CO

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Mentions for John S Mangan

Career records & work history

Lawyers & Attorneys

John Mangan Photo 1

John Mangan - Lawyer

ISLN:
905208723
Admitted:
1984
University:
Manhattan College, B.C.E., 1967
Law School:
Pace University, J.D., 1983
John Mangan Photo 2

John Mangan - Lawyer

Specialties:
Health Care, Personal Injury, Medical Malpractice, Pharmaceuticals & Medical Products, Litigation, Insurance
ISLN:
905208716
Admitted:
1976
University:
University of Kansas, B.A., 1973
Law School:
John Marshall Law School, J.D., 1976
John Mangan Photo 3

John Mangan - Lawyer

Office:
Skadden, Arps, Slate, Meagher & Flom LLP
Specialties:
International Law
ISLN:
905208730
Admitted:
1968
University:
Cornell University, B.C.E., 1964
Law School:
Cornell University, J.D., 1967

John Mangan resumes & CV records

Resumes

John Mangan Photo 41

Ceo At All In Fun Inc.

Position:
CEO at All In Fun Inc.
Location:
United States
Industry:
Events Services
Work:
All In Fun Inc. since Jul 2006
CEO US Army Aug 2001 - Aug 2010
Medical Platoon Sergeant
Education:
University of South Florida 2002 - 2006
B.S., Nursing, Biomedical science
John Mangan Photo 42

John Mangan

Location:
United States
John Mangan Photo 43

John Mangan

Location:
United States
John Mangan Photo 44

John Mangan

Location:
United States

Publications & IP owners

Us Patents

Flash Eeprom System With Simultaneous Multiple Data Sector Programming And Storage Of Physical Block Characteristics In Other Designated Blocks

US Patent:
6426893, Jul 30, 2002
Filed:
Feb 17, 2000
Appl. No.:
09/505555
Inventors:
Kevin M. Conley - San Jose CA
John S. Mangan - Santa Cruz CA
Jeffrey G. Craig - Fremont CA
Assignee:
Sandisk Corporation - Sunnyvale CA
International Classification:
G11C 1604
US Classification:
36518511, 36518904, 36518509
Abstract:
A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.

Method Of Reducing Disturbs In Non-Volatile Memory

US Patent:
6570785, May 27, 2003
Filed:
Oct 31, 2000
Appl. No.:
09/703083
Inventors:
John S. Mangan - Santa Cruz CA
Daniel C. Guterman - Fremont CA
George Samachisa - San Jose CA
Brian Murphy - San Jose CA
Chi-Ming Wang - Fremont CA
Assignee:
SanDisk Corporation - Sunnyvale CA
International Classification:
G11C 1610
US Classification:
36518502, 36518509, 36518512, 36518511
Abstract:
In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an arrays bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the devices application, the rate at which the bit line drivers change the bit line voltage is adjusted.

Flash Eeprom System With Simultaneous Multiple Data Sector Programming And Storage Of Physical Block Characteristics In Other Designated Blocks

US Patent:
6580638, Jun 17, 2003
Filed:
Jun 21, 2002
Appl. No.:
10/176880
Inventors:
Kevin M. Conley - San Jose CA
John S. Mangan - Santa Cruz CA
Jeffrey G. Craig - Fremont CA
Assignee:
SanDisk Corporation - Sunnyvale CA
International Classification:
G11C 1604
US Classification:
36518511, 36518904, 36518509
Abstract:
A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.

Method Of Reducing Disturbs In Non-Volatile Memory

US Patent:
6717851, Apr 6, 2004
Filed:
Jan 10, 2001
Appl. No.:
09/759835
Inventors:
John S. Mangan - Santa Cruz CA
Daniel C. Guterman - Fremont CA
George Samachisa - San Jose CA
Brian Murphy - San Jose CA
Chi-Ming Wang - Fremont CA
Khandker N. Quader - Sunnyvale CA
Assignee:
SanDisk Corporation - Sunnyvale CA
International Classification:
G11C 1604
US Classification:
36518511, 36518512
Abstract:
In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an arrays bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the devices application, the rate at which the bit line drivers change the bit line voltage can be adjusted.

Flash Eeprom System With Simultaneous Multiple Data Sector Programming And Storage Of Physical Block Characteristics In Other Designated Blocks

US Patent:
6760255, Jul 6, 2004
Filed:
Apr 23, 2003
Appl. No.:
10/422216
Inventors:
Kevin M. Conley - San Jose CA
John S. Mangan - Santa Cruz CA
Jeffrey G. Craig - Fremont CA
Assignee:
SanDisk Corporation - Sunnyvale CA
International Classification:
G11C 1604
US Classification:
36518511, 36518509, 36518904
Abstract:
A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.

Method Of Reducing Disturbs In Non-Volatile Memory

US Patent:
6888752, May 3, 2005
Filed:
Jul 1, 2003
Appl. No.:
10/613098
Inventors:
John S. Mangan - Santa Cruz CA, US
Daniel C. Guterman - Fremont CA, US
George Samachisa - San Jose CA, US
Brian Murphy - San Jose CA, US
Chi-Ming Wang - Fremont CA, US
Khandker N. Quader - Sunnyvale CA, US
Assignee:
SanDisk Corporation - Sunnyvale CA
International Classification:
G11C016/04
US Classification:
36518511, 36518512
Abstract:
In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted.

Flash Eeprom System With Simultaneous Multiple Data Sector Programming And Storage Of Physical Block Characteristics In Other Designated Blocks

US Patent:
6996008, Feb 7, 2006
Filed:
May 6, 2004
Appl. No.:
10/841406
Inventors:
Kevin M. Conley - San Jose CA, US
John S. Mangan - Santa Cruz CA, US
Jeffrey G. Craig - Fremont CA, US
Assignee:
SanDisk Corporation - Sunnyvale CA
International Classification:
G11C 16/04
US Classification:
36518511, 36518904, 36518509
Abstract:
A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.

Flash Eeprom System With Simultaneous Multiple Data Sector Programming And Storage Of Physical Block Characteristics In Other Designated Blocks

US Patent:
7184306, Feb 27, 2007
Filed:
Dec 29, 2005
Appl. No.:
11/323576
Inventors:
Kevin M. Conley - San Jose CA, US
John S. Mangan - Santa Cruz CA, US
Jeffrey G. Craig - Fremont CA, US
Assignee:
SanDisk Corporation - Milpitas CA
International Classification:
G11C 16/04
US Classification:
36518511, 36518904, 36518509, 365200, 36518529
Abstract:
A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.

Isbn (Books And Publications)

Life, Character And Influence Of Desiderius Erasmus Of Rotterdam Derived From A Study Of His Works And Correspondence 1927

Author:
John Joseph Mangan
ISBN #:
0766171868

Life, Character And Influence Of Desiderius Erasmus Of Rotterdam Derived From A Study Of His Works And Correspondence 1927

Author:
John Joseph Mangan
ISBN #:
0766171876

Subject Knowledge: Readings For The Study Of School Subjects

Author:
John Marshall Mangan
ISBN #:
0750707267

Subject Knowledge: Readings For The Study Of School Subjects

Author:
John Marshall Mangan
ISBN #:
0750707275

History, Context, And Qualitative Methods In The Study Of Education

Author:
John Marshall Mangan
ISBN #:
0771413696

Distribution Of Income And Wealth

Author:
John Mangan
ISBN #:
0195531930

Life, Character And Influence Of Desiderius Erasmus Of Rotterdam

Author:
John J. Mangan
ISBN #:
0404041787

Possible Relatives

Danny L Mangan  Donald J Mangan  Donna J Mangan  Edward T Mangan  Elizabeth Mangan  Ellen M Mangan  Frank C Mangan  John J Last  John J Stan  John C Stanaway 

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