John Paul Norsworthy, Age 67Woodmoor, CO

6784945, Aug 31, 2004

Oct 1, 1999

09/410588

John P. Norsworthy - Lucas TX
Stanley Vincent Birleson - West Tawakoni TX
Douglas J. Bartek - Frisco TX

Microtune (Texas), L.P. - Plano TX

H04N 550

348731, 348565, 348564

A multiple information decoding system and method are provided in which multiple information content is decoded sequentially and provided to a viewer such that the viewer perceives the information content as being simultaneously decoded. One embodiment of the system and method is in a video display system where RF channels are decoded by a single tuner for concurrent presentation to a display.

5241642, Aug 31, 1993

Sep 28, 1989

7/414139

John P. Norsworthy - Carrollton TX
David T. Stoner - McKinney TX
Michael K. Corry - Plano TX
David M. Pfeiffer - Plano TX

Pixel Semiconductor, Inc. - Plano TX

G06F 1204

395425

There is disclosed a memory controller for controlling addresses to a plurality of different memory types while treating the memory system as a whole so as to create a unified addressing arrangement. The controller is structured to allow for a reprogramming of the split address between the memories and for maintaining contiguously addressed locations. A register is used to hold the split address and the register can be updated at initialization to vary the split depending upon physical memory changes. The controller also maintains a common bit length addressing word regardless of the memory size being addressed by the system processor.

4955024, Sep 4, 1990

Jan 24, 1989

7/301372

David M. Pfeiffer - Plano TX
David T. Stoner - McKinney TX
John P. Norsworthy - Carrollton TX
Dwight D. Dipert - Richardson TX
Jay A. Thompson - Plano TX
James A. Fontaine - Plano TX
Michael K. Corry - Dallas TX

Visual Information Technologies, Inc. - Plano TX

G06F 1110

371 401

Disclosed is an image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28).

6192125, Feb 20, 2001

Jul 1, 1998

9/108576

John Norsworthy - Lucas TX
Darin Kincaid - Coppell TX

Texas Instruments Incorporated - Dallas TX

H04M 100
H04M 1100

379399

There is disclosed a system and method of providing electrical isolation between a telephone line and a connected device, such as a computer. In one embodiment the telephone line is 2-wire and the connected device is 4-wire and includes a feedback elimination circuit. A pair of controlled CTR opto diodes are used in the communication path to effect electrical isolation. The opto diodes are used in conjunction with an electronic inductor constructed using a pair of cascoded darlington transistors to control the telephone line voltage and current and the circuit is designed to maintain the optocouplers within their linear operating range.

5129060, Jul 7, 1992

Jan 24, 1989

7/301373

David M. Pfeiffer - Plano TX
David T. Stoner - McKinney TX
John P. Norsworthy - Carrollton TX
Dwight D. Dipert - Richardson TX
Jay A. Thompson - Plano TX
James A. Fontaine - Plano TX
Michael K. Corry - Dallas TX

Visual Information Technologies, Inc. - Plano TX

G06F 1562

395166

An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) assocated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28).

5146592, Sep 8, 1992

Jan 24, 1989

7/301371

David M. Pfeiffer - Plano TX
David T. Stoner - McKinney TX
John P. Norsworthy - Carrollton TX
Dwight D. Dipert - Richardson TX
Jay A. Thompson - Plano TX
James A. Fontaine - Plano TX
Michael K. Corry - Dallas TX

Visual Information Technologies, Inc. - Plano TX

G06F 1520

395157

An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28).

6144402, Nov 7, 2000

Jul 8, 1997

8/889223

John P. Norsworthy - Lucas TX
Jay A. Thompson - Prosper TX

Microtune, Inc. - Plano TX

H04N 7111

348 13

The invention is a multiple mode transmission system that interconnects the computer of a user with the Internet. The system has a first link that is a relatively low bandwidth telephone system. The system also has a second link that is a relatively high bandwidth television system. The television link can be either terrestrial or cable. The user would send an information request to the Internet across the telephone system. The actual information would be sent to the user via the television system. Scheduling data that informs the user of the time, channel, and exact location of the information in the television signal is sent to the user across the telephone system. The scheduling data is used by the inventive system to program the TV tuner that is used by the computer to receive the TV signal. The information can be encrypted, and the key would be included with the scheduling data. The channels can be dedicated data channels.

5276856, Jan 4, 1994

Sep 28, 1989

7/414106

John P. Norsworthy - Carrollton TX
David T. Stoner - McKinney TX
Michael K. Corry - Plano TX

Pixel Semiconductor, Inc. - Plano TX

G06F 106
G06F 108
G11C 800

395550

There is disclosed a system and method of controlling the timing in a system having a number of different elements, each requiring individual timing signals. The system utilizes a RAM memory divided into a number of groups or cycle types, each cycle type having a number of addressable words. The individual bits of each word serve to control the individual system elements. The memory is programmed to allow each group of words to control the system timing in a different manner. Provision is made for the memory to skip certain words in a particular group under control of externally provided signals.