John R Pastore, Age 5816803 Shipshaw River Dr, Leander, TX 78641

5474958, Dec 12, 1995

May 4, 1993

8/055863

Frank Djennas - Austin TX
Victor K. Nomi - Round Rock TX
John R. Pastore - Leander TX
Twila J. Reeves - Austin TX
Les Postlethwait - Lexington TX

Motorola, Inc. - Schaumburg IL

H01L 2156

437211

A wire bondable plastic encapsulated semiconductor device (58) having no die supporting surface can be manufactured. In one embodiment, a semiconductor die (22) and a plurality of conductors (12) extending toward the periphery of the die are provided. The die is rigidly held in place on a workholder (60) with a vacuum (62) for the wire bonding process. Wire bonds (26) electrically connect the die to the conductors. The wire bonded die is then placed inside a mold cavity (64), and a resin encapsulated is transferred into the cavity under elevated temperature and pressure to form package body (70) around the die, the wire bonds and a portion of the conductors. Before the package body is formed, the die is supported solely by the the rigidity of the wire bonds since there is no die supporting surface connected to the conductors.

5691242, Nov 25, 1997

Feb 26, 1996

8/606981

Victor K. Nomi - Round Rock TX
John R. Pastore - Leander TX
Charles G. Bigler - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 2160

437206

A method for packaging an integrated circuit begins by providing an organic substrate (310) having at least one device site (312). Within each device site, one or more electronic devices (532) is mounted. Around the device site, slots (316) and corner holes (318) are formed. In one embodiment, a negative feature, such as a notch (326), is formed in the substrate along the inner edge (315) of the slots. After the electronic device is mounted and encapsulated in a plastic package body (320), the device is excised from the substrate by punching corner regions of a final package perimeter (317). The placement of the slots, corner holes, and notches results in a punch periphery that is free from burrs, provides maximum active interconnect area, and minimizes surface and/or edge damage during the punch operation. Instead of forming notches, a positive feature, such as a protrusion (426) can be incorporated into a punching tool segment (428) to provide the same benefits.

RE36773, Jul 11, 2000

Nov 14, 1997

8/970272

Victor K. Nomi - Austin TX
John R. Pastore - Leander TX
Twila J. Reeves - Round Rock TX

Motorola, Inc. - Schaumburg IL

H05K 702

361760

Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I/O count for a given substrate area and/or reduces the need to have routing on more than one layer of the substrate.

5287962, Feb 22, 1994

Aug 24, 1992

7/933541

Victor K. Nomi - Round Rock TX
John R. Pastore - Leander TX

Motorola, Inc. - Schaumburg IL

B65D 7302

206328

Plastic encapsulated semiconductor devices are susceptible to moisture due to the permeability of molding compounds. Devices may be baked until dry before being shipped to the customer to reduce the risk of cracking. To retain this dry condition, devices are packaged and shipped in dry-packs. A vacuum seal indicator (18) for flexible material enables a user to determine the integrity of a vacuum seal. The seal indicator has a quick recognition pattern composed of either negative (22) or positive (24) features or a combination thereof, and is placed inside a dry-pack bag (30) which is vacuum sealed prior to shipping. The integrity of the vacuum seal can be determined by looking at the dry-pack bag to see whether the recognition pattern is sharply defined against the bag or not. The vacuum seal indicator can be used in conjunction with any shipping media (28) as long as the outer bag is flexible.

5467252, Nov 14, 1995

Oct 18, 1993

8/136845

Victor Nomi - Round Rock TX
John R. Pastore - Leander TX
Twila J. Reeves - Austin TX

Motorola, Inc. - Schaumburg IL

H05K 702

361760

Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I/O count for a given substrate area and/or reduces the need to have routing on more than one layer of the substrate.

5731709, Mar 24, 1998

Jan 26, 1996

8/592256

John R. Pastore - Leander TX
Victor K. Nomi - Round Rock TX
Howard P. Wilson - Austin TX

Motorola, Inc. - Schaumburg IL

G01R 3102

324760

A ball grid array semiconductor device (30) includes a plurality of conductive balls (36) and a plurality of conductive castellations (18) around its periphery as redundant electrical connections to a semiconductor die (12). During testing of the device in a test socket (50), the conductive castellations are contacted by test contacts (54). The test contacts do not come in physical contact with the conductive balls. As a result, when testing is performed at elevated temperatures near the melting point of the conductive balls, the conductive balls are not deformed by the test contacts, thereby eliminating cosmetic-defects. Additionally, the absence of physical contact between the conductive balls and the test contacts during testing reduces the likelihood that conductive balls will inadvertently fuse to the test socket or create solder build-up on the test contacts.

5285352, Feb 8, 1994

Jul 15, 1992

7/913312

John R. Pastore - Leander TX
Victor K. Nomi - Round Rock TX
Howard P. Wilson - Austin TX

Motorola, Inc. - Schaumburg IL

H05K 720

361707

A pad array semiconductor device (35) includes a thermal conductor (28) integrated into a circuitized substrate (14). A semiconductor die (12) is mounted on the substrate overlying the thermal conductor to establish a thermal path away from the die. The thermal conductor may also be covered or surrounded by a metallized area (37, 39), which together may serve as a ground plane in the device. Preferably one or more terminals (26) are attached to the thermal conductor for improved thermal and electrical performance. One method of integrating the thermal conductor in the substrate is to position a metal plug into an opening 30 of the substrate. The plug is then compressed or otherwise plastically deformed to fill the opening and create a substantially planar substrate surface.