John P Stirniman, Age 6814408 NW 52Nd Ave, Vancouver, WA 98685

John Stirniman Phones & Addresses

14408 52Nd Ave, Vancouver, WA 98685 (360) 546-3934

4810 139Th St, Vancouver, WA 98685 (360) 546-3907

Clatskanie, OR

Hillsboro, OR

Portland, OR

14408 NW 52Nd Ave, Vancouver, WA 98685

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Us Patents

Calculating Etch Proximity-Correction Using Image-Precision Techniques

US Patent:
7207029, Apr 17, 2007
Filed:
Sep 29, 2004
Appl. No.:
10/955189
Inventors:
Dan Beale - Portland OR, US
Jim Shiely - Aloha OR, US
John Stirniman - Vancouver WA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716 21
Abstract:
One embodiment of the present invention provides a system that calculates etch proximity-correction during an OPC (Optical Proximity Correction) process. During operation, the system receives a layout for an integrated circuit. Next, the system selects a target point on an edge in the layout. The system then casts a plurality of rays from the target point, and constructs a plurality of pie-wedges based on the cast rays. The system then computes a surface integral of a statistical function over the pie-wedges, wherein the surface integral of the statistical function models the etch bias at the target point. Next, the calculated etch proximity-correction is applied to an area in proximity to the target point.

Calculating Etch Proximity-Correction Using Object-Precision Techniques

US Patent:
7234129, Jun 19, 2007
Filed:
Sep 29, 2004
Appl. No.:
10/955532
Inventors:
Dan Beale - Portland OR, US
Jim Shiely - Aloha OR, US
John Stirniman - Vancouver WA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716 21, 716 4
Abstract:
One embodiment of the present invention provides a system that calculates etch proximity-correction during an OPC (Optical Proximity Correction) process. During operation, the system receives a layout for an integrated circuit. Next, the system selects a target point on an edge in the layout. The system then creates a list of edges within an ambit of the target point. Next, the system removes edges from the list that are not visible from the target point. The system then computes a line integral of a statistical function over the remaining edges in the list, wherein the line integral of the statistical function models the etch proximity effects correlated with positions of the edges visible from the target point. Next, the calculated etch proximity-correction is applied to an area in proximity to the target point.

Model Of Sensitivity Of A Simulated Layout To A Change In Original Layout, And Use Of Model In Proximity Correction

US Patent:
7458059, Nov 25, 2008
Filed:
Oct 31, 2005
Appl. No.:
11/264298
Inventors:
John P. Stirniman - Vancouver WA, US
Micheal D. Cranford - Hillsboro OR, US
Assignee:
SYNOPSYS, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716 21
Abstract:
A memory is encoded with a model of sensitivity of a distorted layout generated by simulation of a wafer fabrication process, with respect to a change in an original layout that is input to the simulation. The sensitivity model comprises an expression of convolution of the original layout with spatial functions (“kernels”) that are identical to kernels of a process model used in the simulation. A difference between the distorted layout and the original layout is computed, and the difference is divided by a sensitivity value which is obtained directly by evaluating the kemel-based sensitivity model, and the result is used to identify a proximity correction (such as serif size or contour movement) to be made to the original layout. Use of a sensitivity model based on a process model's kernels eliminates a second application of the process model to evaluate sensitivity, thereby to reduce memory and computation requirements.

Flash-Based Anti-Aliasing Techniques For High-Accuracy High Efficiency Mask Synthesis

US Patent:
7617478, Nov 10, 2009
Filed:
Sep 25, 2007
Appl. No.:
11/861191
Inventors:
Michael L. Rieger - Skamania WA, US
Micheal Cranford - Hillsboro OR, US
John P. Stirniman - Vancouver WA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716 21, 716 20
Abstract:
One embodiment of the present invention provides a system that converts a non-bandlimited pattern layout into a band-limited pattern image to facilitate simulating an optical lithography process. During operation, the system receives the non-bandlimited pattern layout which comprises one or more polygons. The system further receives an anti-aliasing filter (AAF) kernel, wherein the AAF kernel is configured to convert a non-bandlimited pattern into a band-limited pattern. The system then constructs an AAF lookup table for the AAF kernel, wherein the AAF lookup table contains precomputed values for a set of convolution functions which are obtained by convolving a set of basis functions with the AAF kernel. Next, the system creates a sampled pattern layout by applying a grid map over the pattern layout. The system then obtains the band-limited pattern image by using the AAF lookup table to convolve the AAF kernel with each grid location in the sampled pattern layout.

Flash-Based Updating Techniques For High-Accuracy High Efficiency Mask Synthesis

US Patent:
7831954, Nov 9, 2010
Filed:
Sep 25, 2007
Appl. No.:
11/861195
Inventors:
Michael L. Rieger - Skamania WA, US
Micheal Cranford - Hillsboro OR, US
John P. Stirniman - Vancouver WA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
G03C 5/00
US Classification:
716 21, 716 1, 716 2, 716 19, 716 20, 430 30
Abstract:
An embodiment of the present invention provides a system that computes the effect of perturbations to a pattern layout during an OPC process. During operation, the system receives a pattern layout and a set of lithography model kernels. The system then obtains a set of convolved patterns by convolving the pattern layout with each of the set of lithography model kernels. The system additionally receives a perturbation pattern to be added onto the pattern layout. Next, for a query location on the pattern layout, the system obtains a set of convolution values at the query location by using model flash lookup tables to convolve the perturbation pattern with the set of lithography model kernels. The system then updates the set of convolved patterns at the query location to account for the effect of the perturbation pattern by combining the set of convolution values with the set of convolved patterns.

Flash-Based Anti-Aliasing Techniques For High-Accuracy High-Efficiency Mask Synthesis

US Patent:
8490032, Jul 16, 2013
Filed:
Sep 28, 2010
Appl. No.:
12/892772
Inventors:
Michael L. Rieger - Skamania WA, US
Micheal Cranford - Hillsboro OR, US
John P. Stirniman - Vancouver WA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
G03F 1/00
US Classification:
716 54, 716 50, 716 51, 716 52, 716 53, 716 55, 716 56, 430 5
Abstract:
Techniques and systems for converting a non-bandlimited pattern layout into a band-limited pattern image are described. During operation, the system receives the non-bandlimited pattern layout which comprises one or more polygons. The system further receives an anti-aliasing filter (AAF) kernel, wherein the AAF kernel is configured to convert a non-bandlimited pattern into a band-limited pattern. The system then constructs an AAF lookup table for the AAF kernel, wherein the AAF lookup table contains precomputed values for a set of convolution functions which are obtained by convolving a set of basis functions with the AAF kernel. Next, the system creates a sampled pattern layout by applying a grid map over the pattern layout. The system then obtains the band-limited pattern image by using the AAF lookup table to convolve the AAF kernel with each grid location in the sampled pattern layout.

Proximity Correction System For Wafer Lithography

US Patent:
6081658, Jun 27, 2000
Filed:
Dec 31, 1997
Appl. No.:
9/001715
Inventors:
Michael L. Rieger - Portland OR
John P. Stirniman - Beaverton OR
Assignee:
Avant! Corporation - Fremont CA
International Classification:
G06F 1750
G21K 1087
US Classification:
39550022
Abstract:
A system for computing a pattern function for a polygonal pattern having a finite number of predetermined face angles. One method includes the steps of decomposing the polygon into a set of flashes, computing the pattern function by summing together all flashes evaluated at a point (x,y), and the pattern function returning a 1 if point (x,y) is inside a polygon and otherwise will return a 0. Another method for computing a two-dimensional convolution value for any point (x,y) on a polygonal pattern includes the steps of identifying a set of half-plane basis functions corresponding to each face angle of the polygonal pattern, convolving each half-plane basis function with a convolution kernel using integration to find convolved flash (cflash) x,y values, storing the cflash (x,y) values to a two-dimensional look-up table, decomposing the polygonal pattern into a set of flashes where each of the flashes is an instance of the half-plane basis functions, and computing a convolution value for point (x,y) by looking-up a corresponding cflash x,y value for each flash in the table and summing together the corresponding cflash x,y values. The present invention may be used in a method for determining correction steps to which a design layout is to be subjected during wafer proximity correction.

Proximity Correction Software For Wafer Lithography

US Patent:
6289499, Sep 11, 2001
Filed:
Jan 7, 2000
Appl. No.:
9/479340
Inventors:
Michael L. Rieger - Portland OR
John P. Stirniman - Beaverton OR
Assignee:
Avant! Corporation - Fremont CA
International Classification:
G06F 1750
G21K 1087
US Classification:
716 21
Abstract:
A system for computing a pattern function for a polygonal pattern having a finite number of predetermined face angles. One method includes the steps of decomposing the polygon into a set of flashes, computing the pattern function by summing together all flashes evaluated at a point (x,y), and the pattern function returning a 1 if point (x,y) is inside a polygon and otherwise will return a 0. Another method for computing a two-dimensional convolution value for any point (x,y) on a polygonal pattern includes the steps of identifying a set of half-plane basis functions corresponding to each face angle of the polygonal pattern, convolving each half-plane basis function with a convolution kernel using integration to find convolved flash (cflash) x,y values, storing the cflash (x,y) values to a two-dimensional look-up table, decomposing the polygonal pattern into a set of flashes where each of the flashes is an instance of the half-plane basis functions, and computing a convolution value for point (x,y) by looking-up a corresponding cflash x,y value for each flash in the table and summing together the corresponding cflash x,y values. The present invention may be used in a method for determining correction steps to which a design layout is to be subjected during wafer proximity correction.

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