Rahul SainiNewark, CA

7010777, Mar 7, 2006

Mar 22, 2004

10/807360

Michael Hutton - Mountain View CA, US
Andy L. Lee - San Jose CA, US
Rahul Saini - Union City CA, US

Altera Corporation - San Jose CA

G06F 17/50

716 19, 716 12, 716 16, 716 17, 326 41

Additional circuitry is provided over a shared-LUT logic circuit to allow functions of different input characteristics to share a logic element which was conventionally illegal. More restrictive circuitry may be provided over a shared-LUT logic circuit to allow functions with particular input characteristics.

7103813, Sep 5, 2006

Nov 6, 2003

10/703400

Paul Tracy - Sunnyvale CA, US
Anthony Pang - San Jose CA, US
Andy Lee - San Jose CA, US
Adam Wright - Saratoga CA, US
Rahul Saini - Union City CA, US

Altera Corporation - San Jose CA

G01R 31/02
G06F 11/267

714725, 716 16

A bridging fault detection system allows for a high amount of test coverage using a low number of test configurations. The bridging fault detection system automatically creates optimal test configurations and test vectors without the need for precise layout information, and is adaptable to complex programmable device architectures. Testers can specify a precise level of testing coverage to optimize the testing processing. A programmable device with interconnect bias circuitry decreases the number of test configurations and thus the time needed to test for bridging faults. The interconnect bias circuit provides explicit test control over the unused lines in a configuration, driving them both high and low for complete test coverage between each line and all of its possible neighbors. The bridging fault detection system balances the available number of control test points against the number of interconnect segments stitched together by programmable connection to maximize the lines under test per configuration.

7167022, Jan 23, 2007

Mar 25, 2004

10/810117

James Schleicher - Los Gatos CA, US
Richard Yuan - Cupertino CA, US
Bruce Pedersen - Sunnyvale CA, US
Sinan Kaptanoglu - Belmont CA, US
Gregg Baeckler - San Jose CA, US
David Lewis - Toronto CA, US
Mike Hutton - Mountain View CA, US
Andy Lee - San Jose CA, US
Rahul Saini - Union City CA, US
Henry Kim - San Jose CA, US

Altera Corporation - San Jose CA

H03K 19/177

326 41, 326 47

Disclosed is an LE that can provide a number of advantageous feature. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

7215140, May 8, 2007

May 30, 2003

10/452673

Rahul Saini - Union City CA, US
Andy Lee - San Jose CA, US
Ninh Ngo - San Jose CA, US

Altera Corporation - San Jose CA

H03K 19/177

326 41, 326 12, 326 47

An embodiment of the present invention provides a programmable logic device (“PLD”) including one or more dedicated blocks of circuitry within one or more repairable logic array regions. Aspects of the present invention provide circuitry and methods for controlling shifting of programming data in normal and redundant modes for both dedicated block regions and fully repairable logic array regions during both regular and test programming sequences of a PLD. Other aspects provide circuitry and methods for interface routing between dedicated blocks and repairable logic array regions in both normal and redundant modes. Various other aspects are also disclosed.

7236411, Jun 26, 2007

Jul 21, 2005

11/187356

Rahul Saini - Union City CA, US
Changsong Zhang - Santa Clara CA, US
David E. Jefferson - Morgan Hill CA, US

Altera Corporation - San Jose CA

G11C 7/00

365194, 365233, 36518905

A programmable device can configure memory access parameters to optimize the performance of one or more of its memory units. A memory unit includes one or more programmable delay units connected with clock, control and/or data signals. The configuration data of the programmable device specifies delay values for each programmable delay unit. A programmable delay unit includes at least two signal paths having different timing characteristics. A switching circuit controlled by configuration data is used to select one of the signal paths as the output of the programmable delay unit. Programmable delay units can be connected in series or in parallel to increase the number of possible delays and/or to specify timing parameters of portions of the memory unit in absolute or relative terms. Programmable delay units can be used to vary the timing characteristics of the memory unit and to control the voltage split used to read data.

7352647, Apr 1, 2008

Dec 22, 2005

11/317324

Rahul Saini - Union City CA, US

Altera Corporation - San Jose CA

G11C 8/00

36523003, 36518901, 36523006

A method and system to reduce power usage of memory within a programmable logic device (PLD) is disclosed. In one embodiment, a memory block is formed from a plurality of memory sub-blocks. A data management circuit is used to programmably couple bitlines and/or wordlines to a selected number of memory sub-blocks necessary for respective read/write operations. During a respective read operation, the data management circuit uses row and/or column addresses to determine which memory bitlines and/or wordlines, and memory sub-blocks are essential in the read operation, leaving other non-essential bitlines and/or wordlines, and memory sub-blocks idle, thereby conserving power usage of the entire memory block. In one embodiment, a during respective read operation, a series of programmable pass-gates are used to selectively de-couple bitlines and/or wordlines, and memory sub-blocks that are not essential to the read operation.

7538579, May 26, 2009

Dec 1, 2006

11/607171

James Schleicher - Los Gatos CA, US
Richard Yuan - Cupertino CA, US
Bruce Pedersen - Sunnyvale CA, US
Sinan Kaptanoglu - Belmont CA, US
Gregg Baeckler - San Jose CA, US
David Lewis - Toronto, CA
Mike Hutton - Mountain View CA, US
Andy Lee - San Jose CA, US
Rahul Saini - Union City CA, US
Henry Kim - San Jose CA, US

Altera Corporation - San Jose CA

H03K 19/177

326 41, 326 40

Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

7671625, Mar 2, 2010

Mar 5, 2008

12/043087

James Schleicher - Los Gatos CA, US
Richard Yuan - Cupertino CA, US
Bruce Pedersen - Sunnyvale CA, US
Sinan Kaptanoglu - Belmont CA, US
Gregg Baeckler - San Jose CA, US
David Lewis - Toronto, CA
Michael Hutton - Mountain View CA, US
Andy Lee - San Jose CA, US
Rahul Saini - Union City CA, US
Henry Kim - San Jose CA, US

Altera Corporation - San Jose CA

H03K 19/177

326 41, 326 38

Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.