Ravikrishna V Cherukuri, Age 595729 La Seyne Pl, San Jose, CA 95138

6345328, Feb 5, 2002

Jun 9, 1999

09/328940

Ranjit J. Rozario - San Jose CA
Sridhar P. Subramanian - Sunnyvale CA
Ravikrishna Cherukuri - Milpitas CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1314

710 52, 710 65, 710 70, 713600, 327144, 326 93

A gear box module or circuit can act as an interface for transferring data from a first clock domain to a second clock domain. The gear box circuit uses a level sensitive memory element coupled to an input selection circuit to receive data from logic in the first clock domain and provide the data to logic in the second clock domain. An input selection signal causes the selection circuit to select the input source for the level sensitive memory element, thereby allowing the proper signal to be provided as output to logic in the second clock domain. Additionally, the gear box can provide the proper output signal for logic in the second domain using circuitry to alternately mask the gear box output. The gear box receives control signals, including for example the input selection signal, from control circuitry. The logic in each clock domain does not have to be aware of the clock frequency on the other side of the gear box, nor does it need to be aware of the ratio of clock frequencies between clock domains.

6381625, Apr 30, 2002

Feb 12, 2001

09/782474

Stuart Oberman - Sunnyvale CA
Norbert Juffa - San Jose CA
Ming Siu - San Jose CA
Frederick D Weber - San Jose CA
Ravikrishna Cherukuri - Milpitas CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 7552

708606, D8605

A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booths algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines.

6397238, May 28, 2002

Feb 12, 2001

09/782475

Stuart Oberman - Sunnyvale CA
Norbert Juffa - San Jose CA
Ming Siu - San Jose CA
Frederick D Weber - San Jose CA
Ravikrishna Cherukuri - Milpitas CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 752

708497, 708551

A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booths algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines.

6618793, Sep 9, 2003

Dec 18, 2000

09/740670

Ranjit J. Rozario - San Jose CA
Ravikrishna Cherukuri - San Jose CA

Redback Networks, Inc. - San Jose CA

G06F 1202

711133, 711 3, 711100, 711118, 711154

Free memory can be managed by creating a free list having entries with address of free memory location. A portion of this free list can then be cached in a cache that includes an upper threshold and a lower threshold. Additionally, a plurality of free lists are created for a plurality of memory banks in a plurality of memory channels. A free list is created for each memory bank in each memory channel. Entries from these free lists are written to a global cache. The entries written to the global cache are distributed between the memory channels and memory banks.

6961822, Nov 1, 2005

Aug 27, 2003

10/650317

Ranjit J. Rozario - San Jose CA, US
Ravikrishna Cherukuri - San Jose CA, US

Redback Networks Inc. - San Jose CA

G06F012/02

711133, 711 3, 711100, 711118, 711154

Free memory can be managed by creating a free list having entries with address of free memory location. A portion of this free list can then be cached in a cache that includes an upper threshold and a lower threshold. Additionally, a plurality of free lists are created for a plurality of memory banks in a plurality of memory channels. A free list is created for each memory bank in each memory channel. Entries from these free lists are written to a global cache. The entries written to the global cache are distributed between the memory channels and memory banks.

6976096, Dec 13, 2005

Jun 2, 2001

09/872936

Ravikrishna V. Cherukuri - San Jose CA, US
Gregory G. Minshall - Albany CA, US

Redback Networks Inc. - San Jose CA

G06F015/16

709250, 709249, 370229, 37039521, 3703953, 37039542

A method and apparatus for controlling the admission of data packets into a network element is described. In an embodiment, a method for controlling admittance of a data packet into a memory buffer includes performing, prior to queuing the data packet for routing by a processor, the following: (1) receiving a data packet from one of at least two different ports, (2) determining a priority value within the data packet, and (3) determining an admittance group identifier for the data packet based on the priority value and the port the data packet was received. The method also comprises queuing the data packet from the memory buffer to one of a number of queues for routing by the processor upon determining that a number of data packets stored in the memory buffer and having the admittance group identifier is not greater than a threshold value.

7007095, Feb 28, 2006

Dec 7, 2001

10/021152

Edmund G. Chen - Sunnyvale CA, US
Ravikrishna Cherukuri - San Jose CA, US
Ruchi Wadhawan - Sunnyvale CA, US

Redback Networks Inc. - San Jose CA

G06F 15/16

709230, 709231, 709238

A method and apparatus for transmitting unscheduled flow control, in packet form, between two chips are described. In one embodiment, a method includes reading a status of a buffer used to receive network packets transmitted from a different chip. The method further includes transmitting to said different chip an unscheduled flow control packet including information about the status of the buffer. In an embodiment, a chip includes a packet buffer to store network packets transmitted from a different chip, wherein the packet buffer is associated with one or more of a plurality of ports through which the network packets travel. The chip also includes control circuitry, coupled with a packet data bus to receive said network packets from the different chip, and coupled with an unscheduled flow control packet bus to generate and transmit unscheduled flow control packets to the different chip, wherein the unscheduled flow control packets contain information relating to the packet buffer.

7020736, Mar 28, 2006

Dec 18, 2000

09/740184

Ravikrishna Cherukuri - San Jose CA, US

Redback Networks Inc. - San Jose CA

G06F 12/00

711 5, 711150, 711157, 711163

A method and apparatus for sharing memory space of multiple memory units by multiple processing units are described. In an embodiment, a method includes storing a set of data across more than one of at least two memory units upon determining that the number of sets of data is static. The method also includes storing the set of data within a single memory unit of the at least two memory units upon determining that the set of data is dynamic.