Ravindranath Tagore Kollipara, Age 64Cupertino, CA

6681338, Jan 20, 2004

Jun 21, 2000

09/599091

Ravindranath T. Kollipara - Fremont CA

Rambus, Inc. - Los Altos CA

G06F 104

713503, 716 12, 711105

Methods and systems for reducing signal skew caused by dielectric material variations within one or more module substrates are described. In one embodiment, an elongate module substrate having a long axis includes multiple signal routing layers supported by the module substrate. Multiple devices, such as memory devices (e. g. DRAMs) are supported by the module substrate and are operably connected with the signal routing layers. Multiple skew-reducing locations (e. g. vias) within the module permit signals that are routed in two or more of the multiple signal routing layers to be switched to a different signal routing layer. The skew-reducing locations can be arranged in at least one line that is generally transverse the long axis of the module substrate. The lines of skew-reducing locations can be disposed at various locations on the module. For example, a line of skew-reducing locations can be disposed proximate the middle of the module to effectively offset skew.

7027307, Apr 11, 2006

Apr 22, 2003

10/420308

Ravindranath T. Kollipara - Fremont CA, US
David Nguyen - San Jose CA, US
Belgacem Haba - Cupertino CA, US

Rambus Inc. - Los Altos CA

H05K 7/02
H05K 7/06
H05K 7/08

361760, 361777, 361775, 327323, 327332, 377 78

An apparatus is provided, which includes a memory interface circuit, a clock signal generating circuit, and a plurality of memory circuits. The memory circuits are operatively coupled and arranged in an order on a plurality of memory modules, such that the memory module positioned at the beginning of the order is coupled to an output of the clock signal generating circuit and the memory interface circuit. The memory module that is positioned at the end of the order is unique in that it includes a clock signal terminating circuit connected to the last memory integrated circuit. With this configuration, a clock loop is formed by directly routing the clock signal from the output of the clock signal generating circuit through each of the memory modules in the order (without connecting to any of the intervening memory integrated circuits) to the memory integrated circuit positioned at the end of the order. Then, the clock signal is asserted on the previous memory modules by routing it back through the memory integrated circuits thereon, in reverse order to the memory integrated circuit positioned at the beginning of the order and from there to the memory interface circuit. To complete the clock loop, the clock signal is again asserted by routing it from the memory interface circuit back through the memory integrated circuits in order to the memory integrated circuit positioned at the end of the order.

8050042, Nov 1, 2011

Jul 26, 2005

11/190561

Ravindranath T. Kollipara - Fremont CA, US
David Nguyen - San Jose CA, US
Belgacem Haba - Cupertino CA, US

Rambus Inc. - Sunnyvale CA

H05K 7/02
H05K 7/06
H05K 7/08
H05K 7/10

361760, 361764, 361784, 361803

The terminating module and method include integrated circuits and a termination circuit which receive clock signals from the integrated circuit. The integrated circuit includes at least one memory integrated circuit mounted on a printed circuit board. An electrical connector is configured to couple the terminating module to a motherboard. Additionally, the termination circuit includes a resistor. In another embodiment, the terminating module provides a printed circuit board, a memory integrated circuit mounted on the circuit board, a terminator circuit which includes a resistor, and an electrical connector. The electrical connector couples the terminating module to a motherboard.

8588012, Nov 19, 2013

Jun 1, 2011

13/149896

John Wilson - Raleigh NC, US
Ravindranath Kollipara - Palo Alto CA, US
David Secker - San Jose CA, US
Kyung Suk Oh - Cupertino CA, US

Rambus, Inc. - Sunnyvale CA

G11C 7/00

365192, 36518905, 326 30, 326 83, 326 26, 326 29

Termination of a high-speed signaling link is effected by simultaneously engaging on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link.

2001004, Nov 15, 2001

Mar 26, 2001

09/817828

Ravindranath Kollipara - Fremont CA, US
David Nguyen - San Jose CA, US
Belgacem Haba - Cupertino CA, US

H05K007/06

361/760000

An apparatus is provided, which includes a memory interface circuit, a clock signal generating circuit, and a plurality of memory circuits. The memory circuits are operatively coupled and arranged in an order on a plurality of memory modules, such that the memory module positioned at the beginning of the order is coupled to an output of the clock signal generating circuit and the memory interface circuit. The memory module that is positioned at the end of the order is unique in that it includes a clock signal terminating circuit connected to the last memory integrated circuit. With this configuration, a clock loop is formed by directly routing the clock signal from the output of the clock signal generating circuit through each of the memory modules in the order (without connecting to any of the intervening memory integrated circuits) to the memory integrated circuit positioned at the end of the order. Then, the clock signal is asserted on the previous memory modules by routing it back through the memory integrated circuits thereon, in reverse order to the memory integrated circuit positioned at the beginning of the order and from there to the memory interface circuit. To complete the clock loop, the clock signal is again asserted by routing it from the memory interface circuit back through the memory integrated circuits in order to the memory integrated circuit positioned at the end of the order. Finally, the clock signal is terminated at the clock signal terminating circuit on the memory module positioned at the end of the order.

2011003, Feb 10, 2011

Nov 12, 2008

12/809517

Jared L. Zerbe - Woodside CA, US
Vladimir M. Stojanovic - Lexington MA, US
Ravindranath Kollipara - Palo Alto CA, US
Wendemagegnehu Beyene - San Jose CA, US
Bruno Garlepp - Sunnyvale CA, US

H04L 27/00

375295

A system comprising: a first integrated circuit device having a multi-band transmission circuit; second and third integrated circuit devices having respective multi-band reception circuits; and a signaling link including a first stub coupled to the multi-band transmission circuit to receive a multi-band signal therefrom, second and third stubs coupled to the multi-band reception circuits of the second and third integrated circuit devices, respectively, to deliver the multi-band signal thereto, and a plurality of channel segments that extend between the first, second and third stubs to convey the multi-band transmission signal therebetween, and wherein at least one of a physical length, impedance or propagation constant of at least one of the first stub, second stub, third stub or channel segment of the plurality of channel segments is selected to spectrally position a frequency-interval exhibiting attenuated frequency response on the signaling link such that multiple passbands separated by the frequency-interval are established to enable conveyance of the multi-band transmission signal on the signaling link.

2011011, May 19, 2011

Jun 30, 2008

12/675105

Ravindranath Kollipara - Palo Alto CA, US
Xingchao Yuan - Palo Alto CA, US
Frank Lambrecht - mountain View CA, US
Ming Li - Fremont CA, US
Richard E. Perego - Thornton CO, US
Qi Lin - Mountain View CA, US
David Nguyen - Cupertino CA, US
Kyung Suk Oh - Campbell CA, US

RAMBUS INC. - Los Altos CA

G06F 13/40
G06F 13/20

710307, 710313

The disclosure relates to a detachable signalling interconnect apparatus that provides connectivity between two or more components of a memory system in conjunction with different modes of operation of the components. The memory system comprises: a first socket to receive a first memory module; a second socket to receive a second memory module; a detachable signal-interconnect; and a memory controller coupled to the detachable signal-interconnect and configured to define a first mode of operation and a second mode of operation, wherein in the first mode of operation the detachable signal-interconnect is to couple the memory-controller to the first memory module and in the second mode of operation the detachable signal-interconnect is to couple the memory controller to the first memory module and the second memory module.

2012000, Jan 5, 2012

Sep 16, 2011

13/235251

Ravindranath T. Kollipara - Fremont CA, US
David Nguyen - San Jose CA, US
Belgacem Haba - Cupertino CA, US

G06F 1/04

327291

The terminating module includes integrated circuits and a termination circuit which receive clock signals from the integrated circuit. The integrated circuit includes at least one memory integrated circuit mounted on a printed circuit board. An electrical connector is configured to couple the terminating module to a motherboard. Additionally, the termination circuit includes a resistor. In another embodiment, the terminating module provides a printed circuit board, a memory integrated circuit mounted on the circuit board, a terminator circuit which includes a resistor, and an electrical connector. The electrical connector couples the terminating module to a motherboard.