Sean L Manion, Age 407750 S Hidden Valley Dr, Boise, ID 83709

Sean Manion Phones & Addresses

7750 S Hidden Valley Dr, Boise, ID 83709 (208) 602-4256

Pullman, WA

Otis Orchards, WA

4465 S Trails End Ln, Boise, ID 83716

Work

Position: Clerical/White Collar

Education

Degree: High school graduate or higher

Mentions for Sean L Manion

Career records & work history

Medicine Doctors

Sean P. Manion

Specialties:
Urology
Work:
UC Health Longmont Clinic
1925 Mtn Vw Ave, Longmont, CO 80501
(303) 776-1234 (phone) (720) 494-3107 (fax)
Longspeak Surgery Center
2030 Mtn Vw Ave STE 100, Longmont, CO 80501
(303) 682-0375 (phone) (303) 682-0593 (fax)
Education:
Medical School
Loyola University Chicago Stritch School of Medicine
Graduated: 1991
Procedures:
Bladder Repair, Cystoscopy, Cystourethroscopy, Kidney Stone Lithotripsy, Prostate Biopsy, Transurethral Resection of Prostate, Urinary Flow Tests, Vaginal Repair, Vasectomy
Conditions:
Benign Prostatic Hypertrophy, Bladder Cancer, Breast Disorders, Calculus of the Urinary System, Cholelethiasis or Cholecystitis, Erectile Dysfunction (ED), Kidney Cancer, Male Infertility, Prostate Cancer, Prostatitis, Urinary Incontinence, Urinary Tract Infection (UT), Varicose Veins
Languages:
English
Description:
Dr. Manion graduated from the Loyola University Chicago Stritch School of Medicine in 1991. He works in Longmont, CO and 1 other location and specializes in Urology. Dr. Manion is affiliated with Longmont United Hospital.

Sean Manion resumes & CV records

Resumes

Sean Manion Photo 28

Senior Ssd R&D Engineer At Micron Technology

Position:
Senior SSD R&D Engineer at Micron Technology
Location:
Boise, Idaho
Industry:
Semiconductors
Work:
Micron Technology since Mar 2011
Senior SSD R&D Engineer
Aptina Imaging Oct 2009 - Mar 2011
Software Engineer
Aptina Imaging Jul 2008 - Oct 2009
Test Development Engineer
Micron Technology May 2007 - Jul 2008
Imaging Test Engineer
Boiler Parts & Chemical Services May 2004 - Aug 2006
Boilermaker
Washington Trust Bank May 2005 - Aug 2005
IT Intern
Education:
Washington State University 2003 - 2007
BS Computer Engineering, Minor in Mathematics
Sean Manion Photo 29

Uw-Stevens Point Graduate And Law Enforcement Recuit Academy Graduate Seeking Opportunities In Law Enforcement In Wi.

Position:
Deputy Reserve Officer at Waupaca County Sheriff's Department
Location:
New London, Wisconsin
Industry:
Law Enforcement
Work:
Waupaca County Sheriff's Department since Jun 2009
Deputy Reserve Officer
New London Parks Department - New London, WI Jun 2011 - Aug 2011
Park Maintenance
Wolfrath's Nursery and Landscape May 2009 - Aug 2010
Garden Center Sales & Service
Oberstadt Landscape and Nursery May 2007 - Aug 2008
Custom Landscape Installer
Education:
Fox Valley Technical College 2011 - 2011
Criminal Justice, Law Enforcement Recruit Academy
University of Wisconsin-Stevens Point 2007 - 2011
B.S., Sociology
Interests:
Hunting, fishing, Taekwondo, guitar
Sean Manion Photo 30

Senior Manager

Location:
Boise, ID
Industry:
Semiconductors
Work:
Micron Technology
Manager - Mnand Competitor Analysis
Micron Technology Dec 2015 - Nov 2017
Senior Design Engineer Supervisor
Micron Technology Mar 2011 - Nov 2014
Software Engineer
Aptina Oct 1, 2009 - Mar 1, 2011
Software Engineer
Aptina Jul 1, 2008 - Oct 1, 2009
Test Development Engineer
Micron Technology May 1, 2007 - Jul 1, 2008
Imaging Test Engineer
Boiler Parts & Chemical Services May 2004 - Aug 2006
Boilermaker
Washington Trust Bank May 1, 2005 - Aug 1, 2005
It Intern
May 1, 2005 - Aug 1, 2005
Senior Manager
Education:
Washington State University 2003 - 2007
Bachelors, Bachelor of Science, Computer Engineering
Skills:
Test Engineering, Perl, Testing, Semiconductors, Jmp, Debugging, Product Engineering, Cmos, Soc, R&D, Software Development, Semiconductor Industry, Python, Website Development
Sean Manion Photo 31

Sean Manion

Sean Manion Photo 32

Sean Manion

Sean Manion Photo 33

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Sean Manion

Publications & IP owners

Us Patents

Sequential Data Optimized Sub-Regions In Storage Devices

US Patent:
2022021, Jul 7, 2022
Filed:
Mar 23, 2022
Appl. No.:
17/702217
Inventors:
- Boise ID, US
Sean L. Manion - Boise ID, US
Jonathan Scott Parry - Boise ID, US
Stephen Hanna - Fort Collins CO, US
Qing Liang - Boise ID, US
Nadav Grosz - Broomfield CO, US
Chistian M. Gyllenskog - Meridian ID, US
Kulachet Tanpairoj - Santa Clara CA, US
International Classification:
G06F 3/06
G06F 12/02
Abstract:
Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

Sequential Data Optimized Sub-Regions In Storage Devices

US Patent:
2021010, Apr 15, 2021
Filed:
Dec 21, 2020
Appl. No.:
17/129087
Inventors:
- Boise ID, US
Sean L. Manion - Boise ID, US
Jonathan Scott Parry - Boise ID, US
Stephen Hanna - Fort Collins CO, US
Qing Liang - Boise ID, US
Nadav Grosz - Broomfield CO, US
Christian M. Gyllenskog - Meridian ID, US
Kulachet Tanpairoj - Santa Clara CA, US
International Classification:
G06F 3/06
G06F 12/02
Abstract:
Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

Sequential Data Optimized Sub-Regions In Storage Devices

US Patent:
2020021, Jul 2, 2020
Filed:
Dec 31, 2018
Appl. No.:
16/237134
Inventors:
- Boise ID, US
Sean L. Manion - Boise ID, US
Jonathan Parry - Boise ID, US
Stephen Hanna - Fort Collins CO, US
Qing Liang - Boise ID, US
Nadav Grosz - Broomfield CO, US
Christian M. Gyllenskog - Meridian ID, US
Kulachet Tanpairoj - Santa Clara CA, US
International Classification:
G06F 3/06
G06F 12/02
Abstract:
Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

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