Stephen S MaElk Grove, CA

6954463, Oct 11, 2005

Dec 11, 2000

09/735280

Stephen Ma - Santa Clara CA, US
Suresh Sangiah - Fremont CA, US
Jagannadh Tangirala - Campbell CA, US
R. Ashby Armistead - Los Altos CA, US

Cisco Technology, Inc. - San Jose CA

H04L012/28

370401, 370392

An access server architecture, and methods for use of the architecture, are disclosed. The architecture and methods are designed to increase the scalability of and balance processor load for a network access server. In this architecture, packet forwarding and packet processing are distributed amongst the cards serving the low-speed access lines, such that each line card is responsible for performing forwarding and packet processing for packets associated with the low-speed ports that line card serves. As the number of line cards expands, forwarding resources are expanded in at least rough proportion. The NAS route switch controller, and the high-speed ports, are largely relieved of packet processing tasks because the egress port uses a distribution engine that performs a cursory examination on one or more header fields on packets received—comprehending only enough information to allow each packet to be distributed to the appropriate line card for full processing.

7606245, Oct 20, 2009

Aug 18, 2005

11/207435

Stephen Ma - Santa Clara CA, US
Suresh Sangiah - Fremont CA, US
Jagannadh Tangirala - Campbell CA, US
R. Ashby Armistead - Los Altos CA, US

Cisco Technology, Inc. - San Jose CA

H04L 12/28

370401, 370392, 370352, 370356, 709229

An access server architecture, and methods for use of the architecture, are disclosed. The architecture and methods are designed to increase the scalability of and balance processor load for a network access server device. In this architecture, packet forwarding and packet processing are distributed amongst the cards serving the low-speed access lines, such that each line card is responsible for performing forwarding and packet processing for packets associated with the low-speed ports that line card serves. As the number of line cards expands, forwarding resources are expanded in at least rough proportion. The NAS route switch controller, and the high-speed ports, are largely relieved of packet processing tasks because the egress port uses a distribution engine that performs a cursory examination on one or more header fields on packets received—comprehending only enough information to allow each packet to be distributed to the appropriate line card for full packet processing.

7616646, Nov 10, 2009

Dec 12, 2000

09/735718

Stephen Ma - Santa Clara CA, US
Suresh Sangiah - Fremont CA, US
Jagannadh Tangirala - Campbell CA, US
R. Ashby Armistead - Los Altos CA, US

Cisco Technology, Inc. - San Jose CA

H04L 12/28

370401, 370392

An access server architecture, and methods for use of the architecture to increase the scalability of and balance processor load for a network access server device, are disclosed. In this architecture, packet forwarding and packet processing are distributed amongst cards serving low-speed access lines (i. e. , line cards). Thus, as the number of line cards expands, forwarding resources are expanded in at least rough proportion. The NAS route switch controller and the high-speed ports used to access the network are largely relieved of packet processing tasks for traffic passing through the server. The egress port uses a distribution engine that performs the routing lookup for packets received at the high-speed interface, tags the packets with an adjacency table pointer, and sends them to the appropriate forwarding engine for packet processing. The route switch controller, largely uninvolved in the processing of packets, updates routing information needed by each distribution or forwarding engine.