Siu M Tsang, Age 616214 Mesa Grande, Austin, TX 78749

4000413, Dec 28, 1976

May 27, 1975

5/580629

Sau Ching Wong - San Francisco CA
Siu Keun Tsang - San Francisco CA

Intel Corporation - Santa Clara CA

H03K 3353
H03K 513
H03K 518
H03K 3286

307208

Improved circuits for a MOS-RAM including an on chip TTL compatible high-level clock driver and sense amplifier. The driver employs a unique feedback and delay scheme allowing the high-level line to be quickly and efficiently discharged without using a large, high capacitance device. The upward swing of the control signal for the sense amplifier includes a perturbation which increases the sensitivity of the amplifier.

4837748, Jun 6, 1989

Apr 14, 1987

7/038107

Shine C. Chung - San Jose CA
Siu K. Tsang - San Jose CA
James T. Koo - Los Altos Hills CA
Sho Long S. Chen - Palo Alto CA
John Y. Chan - San Carlos CA

Vitelic Corporation - San Jose CA

G11C 800

365236

An integrated circuit memory with additional circuitry added so that the integrated circuit acts as a counting memory is disclosed. A memory core is included with associated circuitry allowing it to be accessed in the same manner as ordinary random access memory (RAM). A counter is included and is coupled so that it can receive the contents of any location in the memory core. Each address in the memory acts as an individual counter. When a particular memory address is presented indicating that the count at that memory location should be incremented, the contents of that memory location are transferred to the counter, the counter is incremented, and the contents of the counter are then transferred back to the memory location. This process is repeated each time a new address is presented indicating a new event to be recorded. At the end of a series of events, the core memory will contain, at each corresponding memory location, the number of occurrences of the event assigned to that address.

5630163, May 13, 1997

May 26, 1995

8/452246

Henry T. Fung - San Jose CA
Siu K. Tsang - San Jose CA
Phillip M. Mitchell - Milpitas CA
Norman P. Farquhar - San Jose CA

Vadem Corporation - San Jose CA

G06F 1300

395800

A data processing system including a central processing unit and control circuitry on a single chip connected by a common bus to two or more bus devices having different sets of bus parameters. A first set of bus parameters functions as a memory bus for transfers to and from main memory, a second set of bus parameters functions as an I/O bus for I/O device transfers and a third set of bus parameters functions as a video bus for transfers to a video display. Each set of bus parameters has different timing selected to maximize transfers for the particular bus function (main memory, I/O, video or other) implemented by the bus parameters.

5337408, Aug 9, 1994

Dec 30, 1991

7/815928

Henry T. Fung - San Jose CA
Siu K. Tsang - San Jose CA
Ralph A. Woodward - Mountain View CA

Vadem Corporation - San Jose CA

G06F 300

395162

Disclosed is a computer having a display controller for controlling a display where the display provides an image with different selectable gray scale levels. The display controller includes a pattern unit for providing modulation patterns. The modulation patterns include patterns each formed of sequences of different numbers of both 1's and 0's that are not phase related. The display controller additionally includes a modulation unit, operable over the sequential frames, for modulating the data values of pixels with the patterns whereby the intensity level of the pixels over the sequential frames is controlled as a function of the data value of the pixels and as a function of the patterns.

4376300, Mar 8, 1983

Jan 2, 1981

6/221316

Siu K. Tsang - San Jose CA

Intel Corporation - Santa Clara CA

G11C 1140

365200

A memory system is described which employs a plurality of "mostly good" memory chips. A redundant memory chip is used to store data designated to the defective locations in the mostly good memories. In one embodiment a PROM is programmed to recognize the addresses of the defective elements and to cause the redundant memory to be selected. In another embodiment, a content-addressable memory is employed to provide a new address in response to the addresses of defective elements in the mostly good memories.

4247917, Jan 27, 1981

Aug 27, 1979

6/070132

Siu K. Tsang - San Jose CA
Carl J. Simonsen - Aloha OR
William M. Holt - Aloha OR

Intel Corporation - Santa Clara CA

G11C 700
G11C 706

365205

An MOS dynamic random-access memory (RAM) realizable as a 64K RAM is disclosed. Single transistor cells employing capacitive storage are coupled to folded bit-line halves. These bit-line halves are connected to sense amplifiers employing cross-coupled transistors. Boosting means employing a variable capacitance are coupled to the bit-line halves to boost the potential on a line during reading. The capacitor associated with each of the memory cells is coupled to a potential which is greater than the power supply potential. This plate potential is substantially constant and independent of power supply variations and is internally generated. The dummy cells employed within the RAM are charged in a unique manner to a substantially constant potential which does not vary with power supply variations.

5961617, Oct 5, 1999

Aug 18, 1997

8/914846

Siu Keun Tsang - Saratoga CA

Vadem - San Jose CA

G06F 1300
G06F 132

710100

A system and method are described that reduce display subsystem power consumption in computer systems where image data is transferred from an image memory to a display each time a new image frame is displayed. In normal operation, the computer system displays uncompressed image data, which is stored in the image memory. After a period of display inactivity, a display processor compresses the uncompressed data and writes the compressed data to another location in the image memory. In subsequent display cycles, until there is display activity, the display processor retrieves the compressed data from the memory, decompresses it in real time and then transfers the decompressed data to the display. Entire images or segments of images can be compressed in this manner. Using the compressed image data saves display power as it requires fewer memory cycles to transfer from the memory to the display than the uncompressed data.