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Krishna Srinivasan6152 Oakland St, Chandler, AZ 85226

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Known as:
Krishna M Sprinivasan Krishna M Srinivasan K Srinivasan

Krishna Srinivasan Phones & Addresses

6152 Oakland St, Chandler, AZ 85226 (480) 940-9140

6152 W Oakland St #274, Chandler, AZ 85226 (480) 940-9140

Atlanta, GA

6152 W Oakland St APT 274, Chandler, AZ 85226 (480) 818-3368

Work

Position: Sales Occupations

Education

Degree: Associate degree or higher

Mentions for Krishna Srinivasan

Krishna Srinivasan resumes & CV records

Resumes

Krishna Srinivasan Photo 34

Packaging Design Engineer

Location:
Chandler, AZ
Industry:
Semiconductors
Work:
Intel Corporation
Packaging Design Engineer
Krishna Srinivasan Photo 35

Krishna Srinivasan

Krishna Srinivasan Photo 36

Krishna Srinivasan

Krishna Srinivasan Photo 37

Director Of Operations

Work:

Director of Operations
Krishna Srinivasan Photo 38

Krishna Srinivasan

Location:
United States

Publications & IP owners

Us Patents

Device Having An Array Of Embedded Capacitors For Power Delivery And Decoupling Of High Speed Input/Output Circuitry Of An Integrated Circuit

US Patent:
7705423, Apr 27, 2010
Filed:
Sep 19, 2006
Appl. No.:
11/523270
Inventors:
Madhavan Swaminathan - Marrietta GA, US
Ege Engin - Atlanta GA, US
Prathap Muthana - Atlanta GA, US
Krishna Srinivasan - Atlanta GA, US
Assignee:
Georgia Tech Research Corporation - Atlanta GA
International Classification:
H01L 29/00
US Classification:
257532, 257312, 257700, 257723, 257724, 257924, 257E23062, 257E2307, 257E23079
Abstract:
One embodiment of the present invention provides advice for providing a low noise power supply package to an integrated circuit comprising a semiconductor die, input/output power supply terminals, and an array of embedded ceramic capacitors selected from discrete, planar and combinations thereof wherein said capacitors are placed in the locations selected from within the perimeter of the shadow of the semiconductor die, partially within the perimeter of the shadow of the semiconductor die, near the perimeter of the shadow of the semiconductor die, and combinations thereof.

Integrated Circuit Package With Through Void Guard Trace

US Patent:
2019029, Sep 26, 2019
Filed:
Mar 23, 2018
Appl. No.:
15/934191
Inventors:
- Santa Clara CA, US
Krishna SRINIVASAN - Chandler AZ, US
Arnab SARKAR - Chandler AZ, US
International Classification:
H01L 23/00
H01L 23/525
Abstract:
Apparatuses, systems and methods associated with over void signal trace design are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first layer that has a void and a guard trace, wherein a first portion of the void is located on a first side of the guard trace and a second portion of the void is located on a second side of the guard trace. The IC package may further include a second layer located adjacent to the first layer, wherein the second layer has a signal trace that extends along the guard trace. Other embodiments may be described and/or claimed.

High Density Package Interconnects

US Patent:
2019017, Jun 6, 2019
Filed:
Jan 29, 2019
Appl. No.:
16/261475
Inventors:
- Santa Clara CA, US
Zhiguo QIAN - Chandler AZ, US
Robert L. SANKMAN - Phoenix AZ, US
Krishna SRINIVASAN - Chandler AZ, US
Zhaohui ZHU - Tempe AZ, US
International Classification:
H01L 23/498
H01L 23/00
H01L 21/768
H01L 23/50
Abstract:
Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

High Density Package Interconnects

US Patent:
2018018, Jun 28, 2018
Filed:
Feb 20, 2018
Appl. No.:
15/900696
Inventors:
- Santa Clara CA, US
Zhiguo QIAN - Chandler AZ, US
Robert L. SANKMAN - Phoenix AZ, US
Krishna SRINIVASAN - Chandler AZ, US
Zhaohui ZHU - Tempe AZ, US
International Classification:
H01L 23/498
H01L 23/50
H01L 21/768
H01L 23/00
H01L 23/538
Abstract:
Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

High Density Package Interconnects

US Patent:
2016028, Sep 29, 2016
Filed:
Jun 6, 2016
Appl. No.:
15/174921
Inventors:
- Santa Clara CA, US
Zhiguo QIAN - Chandler AZ, US
Robert L. SANKMAN - Phoenix AZ, US
Krishna SRINIVASAN - Chandler AZ, US
Zhaohui ZHU - Tempe AZ, US
International Classification:
H01L 23/498
H01L 23/00
H01L 23/50
Abstract:
Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

High Density Package Interconnects

US Patent:
2014021, Aug 7, 2014
Filed:
Dec 31, 2011
Appl. No.:
13/977658
Inventors:
Sanka Ganesan - Chandler AZ, US
Zhiguo Qian - Chandler AZ, US
Robert L. Sankman - Phoenix AZ, US
Krishna Srinivasan - Chandler AZ, US
Zhaohui Zhu - Tempe AZ, US
International Classification:
H01L 23/498
H01L 21/768
US Classification:
257737, 438613
Abstract:
Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

Amazon

Krishna Srinivasan Photo 42

Vietnam: Transition To A Market Economy (Occasional Paper (Intl Monetary Fund))

Author:
John R. Dodsworth, Erich Spitaller, Michael Braulke, Keon Kyok Lee, Kenneth Miranda, Christian Mulder, Hisanobu Shishido, Krishna Srinivasan
Publisher:
Intl Monetary Fund
Binding:
Paperback
Pages:
58
ISBN #:
1557755388
EAN Code:
9781557755384
Krishna Srinivasan Photo 43

Vietnam: Transition To A Market Economy (Occasional Paper (Intl Monetary Fund))

Author:
Krishna Srinivasan, Erich Spitäller, M. Braulke, Christian B. Mulder, Hisanobu Shishido, Kenneth M. Miranda, John Dodsworth, Keon Lee
Publisher:
INTERNATIONAL MONETARY FUND
Binding:
Kindle Edition
Pages:
58
The paper explores the pattern of transition of the Vietnamese economy, the policies that were applied, and the reasons for the country's success. In particular, it focuses on output performance; state-owned enterprises; foreign direct investment; determinants of inflation; dollarization and problem...
Krishna Srinivasan Photo 44

Unconventional Choices For Unconventional Times Credit And Quantitative Easing In Advanced Economies

Author:
Vladimir Klyuev, Phil De Imus, Krishna Srinivasan
Publisher:
INTERNATIONAL MONETARY FUND
Binding:
Kindle Edition
Pages:
57
This paper discusses the scale and scope of unconventional measures adopted by major central banks across different countries during financial crises. When the September 2008 crisis intensified, central banks found their traditional tools insufficient to deal with the collapse of key credit markets....
Krishna Srinivasan Photo 45

Global Rebalancing: A Roadmap For Economic Recovery

Publisher:
Intl Monetary Fund
Binding:
Paperback
Pages:
170
ISBN #:
1475573669
EAN Code:
9781475573664
This book examines imbalances in seven major economies: China, France, Germany, India, Japan, the United Kingdom, and the United States, evaluating key indicators agreed on by the G20 for identifying large imbalances, including public and private debt and private saving, and countries' external posi...
Krishna Srinivasan Photo 46

This Is Not Available 009146

Author:
Krishna Srinivasan
Publisher:
ProQuest, UMI Dissertation Publishing
Binding:
Paperback
Pages:
156
ISBN #:
1243532335
EAN Code:
9781243532336
This book is not available.
Krishna Srinivasan Photo 47

The Perils Of Foreign Capital?: An Article From: Finance & Development

Author:
Krishna Srinivasan
Publisher:
International Monetary Fund
Binding:
Digital
Pages:
2
This digital document is an article from Finance & Development, published by International Monetary Fund on December 1, 2003. The length of the article is 482 words. The page length shown above is based on a typical 300-word page. The article is delivered in HTML format and is available in your Amaz...
Krishna Srinivasan Photo 48

The Philosophy Of Small Scale Industrial Management,

Author:
Krishna Srinivasan Iyengar
Publisher:
Today & Tomorrow's Printers & Publishers
Binding:
Unknown Binding
Pages:
195

Possible Relatives

Ganesan Srinivasan  Jaya L Srinivasan  Jayaram S Srinivasan  Kumar S Srinivasan  Lakshmi Srinivasan  Mahesh S Srinivasan  Marycarmen C Srinivasan  Krishna B Patel  Krishna Brown  Krishna G Rao 

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